EPM7064STC44-7N Altera

Xilinx CPLDs (Complex Programmable Logic Devices) XC2C256-7TQG144C is a 6.7ns CPLD with a surface mount package. It is designed to operate in temperatures ranging from 0°C to 70°C (TA). It is packaged in a tray and is in-system programmable. It has 144-TQFP (20x20) package. Features: • 6.7ns CPLD • Surface mount package • Operating temperature range of 0°C to 70°C (TA) • Tray package • In-system programmable • 144-TQFP (20x20) package Applications: Xilinx CPLDs (Complex Programmable Logic Devices) XC2C256-7TQG144C can be used in a variety of applications such as: • Automotive • Industrial • Medical • Aerospace • Consumer electronics • Networking and communications • Military and defense

Lattice CPLDs (Complex Programmable Logic Devices) are programmable logic devices that are used to implement complex logic functions. They are used in a variety of applications, including embedded systems, automotive, industrial, and consumer electronics. They are used to create custom logic functions, such as state machines, counters, and shift registers. They are also used to create custom interfaces between different devices, such as microcontrollers and memory devices. They are also used to create custom logic functions for digital signal processing applications.

The XILINX XC9536XL-10PCG44C is a Complex Programmable Logic Device (CPLD) with 10.0ns access time and a temperature range of 0°C to 70°C (TA). It is a 44-PLCC (16.59x16.59) package and is in system programmable with a minimum of 10K program/erase cycles. Features: • 10.0ns access time • 0°C to 70°C (TA) temperature range • 44-PLCC (16.59x16.59) package • In system programmable with a minimum of 10K program/erase cycles Applications: The XILINX XC9536XL-10PCG44C CPLD is suitable for a wide range of applications, including: • Automotive • Industrial • Medical • Networking • Telecommunications • Consumer electronics • Aerospace and defense

The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. Features ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture ■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 ■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices ■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells ■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)