NC7SZ08P5X onsemi

The TI Gates and Inverters SN74LVC1G08DRLR is a single-gate AND gate surface mount device designed for use in a wide range of applications. This device is capable of operating over a temperature range of -40°C to 125°C and is available in a Digi-Reel alternate packaging. It features a low power consumption of 10μA and is powered by a 5.5 V supply voltage. The device is housed in a SOT-5 package and is ideal for use in low-power applications. It is also suitable for use in automotive, industrial, and consumer applications. The device is designed to provide reliable performance and is backed by TI's quality assurance.

The Intersil ISL317XE are ±15kV IEC61000 ESD Protected, 3.3V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. These devices have very low bus currents (+125μA/-100μA), so they present a true “1/8 unit load” to the RS-485 bus. This allows up to 256 transceivers on the network without violating the RS-485 specification’s 32 unit load maximum, and without using repeaters. For example, in a remote utility meter reading system, individual meter readings are routed to a concentrator via an RS-485 network, so the high allowed node count minimizes the number of repeaters required.

TheB Series logic gates are constructed with P and N channel enhancementmode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired.

The MC14106B hex Schmitt Trigger is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. The MC14106B may be used in place of the MC14069UB hex inverter for enhanced noise immunity or to “square up” slowly changing waveforms.This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤(Vin or Vout) ≤ VDD.Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.