The CAN-PCIe/402-FD is a PC board designed for the PCIe bus that features one or two electrically isolated CAN FD interfaces according to ISO 11898-2 via DSUB9 connectors. Equipped with up to two CAN FD interfaces the board is available as low profile versions. In the CAN-PCIe/402-B4-FD version 4 CAN FD interfaces can be connected via one 37-pin DSUB connector. The CAN FD interfaces are designed according to ISO 11898-1:2015. They are driven by the ISO 16845:2004 certified esdACC (esd advanced CAN Core), implemented in the Intel FPGA. All CAN FD versions are fully backwards compatible with CAN and can also be used in Classical CAN applications. The FPGA supports bus mastering (first-party DMA) to transfer data to the host memory. This results in a reduction of overall latency on servicing I/O transactions in particular at higher data rates and a reduced host CPU load.
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CAN FD (CAN flexible data rate) is an expasion of the “classical” CAN bus (CAN classic) and is defined by the standard ISO 11898-1:2015. CAN FD facilitates not only sending of larger data volumes (payload): the limit of 8 bytes with CAN classic has been increased to 64 bytes with CAN FD. Also, it provides the possibility of a higher bit rate within the data phase, even going beyond the previous limit of 1 MBit/s.
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